This invention relates generally to semiconductor memory devices, and more specifically to read only memory ROM and antifuse-based programmable read only memory (PROM) cells having improved ON and OFF characteristics that allow advanced levels of microminiaturization. The invention especially relates to the concurrent fabrication of high quality isolation diodes and low resistance buried (lower) wiring layers used typically as bit lines in memory matrices.
Certain nonvolatile memories that incorporate Schottky barrier diodes are based on antifuse memory cells (elements that act opposite to fuses). The antifuse memory cells typically comprise an intrinsic silicon (defined as silicon with negligible impurities) film deposited over a Schottky barrier diode (see, FIG. 3). Such memory cells have a substrate 1, a first insulation layer 2, a polycrystalline silicon film (polysilicon layer) 5, a second insulation layer 7, a titanium layer 8, an intrinsic silicon film 9, and an aluminum interconnect 10. A Schottky barrier diode is created at the interface of the polysilicon layer 5 and the titanium layer 8 that is deposited on layer 5.
Individual memory cells are often arranged in matrices to get the smallest possible memory array size. FIG. 4 is an example of such a matrix. Each cell is equivalent to a programmable switch in series with an isolation diode. The data stored is represented by the switch either being ON and OFF. The diodes in FIG. 4 are Schottky barrier diodes. Silicon film 9 has a high resistance before being programmed. Such a condition in an antifuse cell is often spoke of as the OFF (unprogrammed) state. This is opposite to fuse link type PROMs where the fuses are blown open by programming to be in their OFF state. To program an antifuse memory cell, a voltage of about 20 volts is applied across silicon film 9, this causes a dielectric breakdown to occur with a resulting current flow that forms a conductive bridge (by a mechanism not fully understood by those skilled in the art).
Attempts to further microminiaturize antifuse memory cells of the prior art have encountered major structural problems. At very fine geometries, large variations in data read sensing currents occur due to the necessary arrangement of memory cells into a matrix. FIG. 3 is a prior art antifuse memory cell comprised of a substrate 1, an insulating layer 2, a polysilicon layer 5 that serves double duty as a bit line interconnect, a second insulating layer 7, a refractory metal layer 8 that forms a Schottky barrier diode interface with polysilicon layer 5, an intrinsic silicon layer 9 that is so pure it functions as an insulator until a programming voltage is applied and changes its structure, and an aluminum metalization 10 that serves as a word line interconnect. FIG. 4 shows sixteen memory cells positioned at the intersections of four bit lines and four word lines. As mentioned, the bit lines (vertical lines in FIG. 4) are typically made of the n-polysilicon layer 5, and as such it needs to have high doping levels in order to be sufficiently conductive. But too high a level of doping will disable the Schottky barrier diode. The word line select lines (horizontal lines in FIG. 4) use the aluminum interconnect 10. Although the sheet resistance value of the aluminum is under 30 milli-ohms/square, the sheet resistance of silicon with a high impurity level that is still low enough to be compatible with a Schottky barrier diode is very high, usually over 1,000 .OMEGA./square. Higher levels of impurities (over 1.times.10.sup.22 cm.sup.-3) can be injected to lower the resistance value to about 100 .OMEGA./square. But the diffusion current (the reverse biased current in the Schottky barrier diode) gets too high, and the diode ceases to effectively isolate the memory cells from one another. The parasitic resistance values also vary greatly as a function of the positions of the cells from the current sensing circuit. Even cells programmed the same way will show great differences in sense current if one cell is close to and the other cell is relatively far from the current sensing circuit. This complicates programmed data sensing and makes data reading difficult.
Further variability in read sensing currents also stems from the fact that the greater the current during programming of a memory cell, the lower an ON resistance that cell will have during reading. The farthest out cells receive the least amount of programming current and return the least amount of read current for two reasons. The first was just mentioned and the second is that the read sense bit line lines add their own resistance to the read current.
To combat this problem, the prior art has had to make the polysilicon lines wider, but this runs contrary to efforts to microminiaturize PROM memories beyond present day levels.
A prior art memory cell in FIG. 7 has a substrate 21, a first insulation layer 22, a lower layer wiring 34 (e.g., polycrystalline silicon film containing a high impurity concentration), a semiconductor film 33 (e.g., polycrystalline film containing impurity on the order of 1.times.10.sup.17 atoms per cm.sup.-3), a second insulation film 29, a metal film 32, e.g., titanium or platinum, an intrinsic silicon film 30 (e.g., impurity-free polycrystalline film), and a wiring layer 31 (e.g., aluminum film). The intrinsic silicon film 30 is formed on top of what constitutes a Schottky barrier diode. The diode comprises metal film 32 and semiconductor film 33. When programmed, the memory cell will connect wiring layer 31 through film 30 to the metal 32 side of the Schottky diode. The intrinsic silicon film 30 acts as an insulator before programming. Programming applies a voltage of about 20 V across the intrinsic silicon film, a dielectric breakdown occurs in the intrinsic silicon film and current flows causing structural changes that permanently short across layer 10.
In the prior art there are problems that occur during heat treatment. Impurities from (for example FIG. 7) layer 34 can migrate into the semiconductor film 33, which is part of a Schottky barrier diode, that causes deterioration in the performance of the Schottky barrier diode. A conventional way to further microminiaturize a memory cell has been to make the lower layer wiring 34 a silicon film have a high concentration impurity (over 1.times.10.sup.21 atoms per cm.sup.-3). Silicon film can be made very thin. Semiconductor film 33 is injected with a small amount of impurity. Heat treatment is used to activate the impurities. At this point, impurities in the lower layer wiring 34 will surge into the semiconductor film 33 during programming, and will end up in the metal film 32. The distance between layer wiring 34 and the metal film 32 (the film thickness of the semiconductor film 33) is very small. An acceptable concentration of impurities (such as phosphorus, boron, or arsenic) for semiconductor film 33 is 1.times.10.sup.20 atoms per cm.sup.-3. If the concentration gets too high, there is a problem with reverse current (diffusion current) in the Schottky barrier diode that gets too high. Experiments have shown that the difference in absolute values of the ON current and OFF current are as much as six orders of magnitude. But, if impurities are allowed to get to the metal film, the figure drops to less than one order of magnitude. When such a cell is fabricated as an antifuse-based PROM cell, current from other memory cells cannot be isolated.
Another prior art memory device is illustrated in FIG. 10, and it comprises a substrate 41, a first insulation layer 42, a lower layer wiring layer 43 (e.g., polycrystalline silicon containing impurity in high concentration), a semiconductor film 44 (e.g., polycrystalline silicon containing impurity on the order of 1.times.10.sup.17 atoms per cm.sup.-3), a second insulation film 45, a metal film 46 (e.g., titanium or platinum), an intrinsic silicon film 47 (e.g., a polycrystalline silicon film that does not contain impurities), and a wiring layer 48 (e.g., aluminum film). Much of the structure has been described above. But FIG. 10 shows a sectional view of three cells.
FIG. 12A to FIG. 12E show a prior art method of manufacturing a memory cell. In FIG. 12A, a first insulation layer 122 of SiO.sub.2 film is deposited 3,000 .ANG. thick on a substrate 121 with a chemical vapor deposition (CVD) method or a hot oxidation method in an oxygen atmosphere. A silicon film 123 is next deposited 5,000 .ANG. thick with a CVD method leaving a polycrystalline silicon film by pyrolyzing monosilane gas at a temperature of about 620.degree. C. Then a group V element (for example phosphorus or arsenic) is injected to make n-type region 128. A conventional ion driving method is used. The dose amount should be about 1.times.10.sup.14 atoms per cm.sup.-2. In FIG. 12B, the unnecessary parts of silicon film 123 are removed by a conventional photo-etching method. In FIG. 12C, a resist mask 125 is formed outside the area of where a p-type region 129 will be. A group III element (boron for example) is then injected, driven by a conventional ion driving method, with a dosage level higher than the dosage level for the group V element, about 1.times.10.sup.15 atoms per cm.sup.-2. Therefore, the n-type region 128 is eliminated to make p-type region 129. In FIG. 12D, the resist mask 125 is removed, and a second insulation layer 127 of SiO.sub.2 film is deposited 2,000 .ANG. thick using a CVD method. A heat treatment follows to activate the group V and group III impurities. Annealing is preferably then done at 1,000.degree. C. for one minute in a nitrogen atmosphere using a halogen lamp. Next, contact holes 130 are positioned in the second insulation layer 127 in n-type region 128 and p-type region 129 using a photo-etching method. In FIG. 12E, aluminum is deposited with a sputtering method to produce a wiring layer 131 on top of the second insulation layer 127 and contact holes 130. Unnecessary portions of layer 131 are removed with a photo-etching method. A P-N junction diode is thus constructed at the interface of regions 128 and 129.
A few prior art read only memory (ROM) devices are programmed by an ion injection method to change the value of the threshold voltage of single transistor cells, like the one shown in FIG. 18A. (See, Y. Shacham-Diamand, et al., "A NOVEL ION-IMPLANTED AMORPHOUS SILICON PROGRAMMABLE ELEMENT", IEDM 87, pp. 194-197.) In FIG. 18B, such a device comprises a substrate 281, a gate film 282, a gate electrode 283, a high concentration diffusion layer 284, an LDD-type low concentration diffusion layer 285, an LDD-type side wall insulation film 286, an interlayer insulation film 287, and an aluminum wiring layer 288. Here the ROM data write-in is done by forming impurity layer 289 by ion injection before or after forming interlayer insulation film 287 to change the threshold voltage. Also, FIG. 18C is a plan view, where "A" is a single memory cell unit and space 290 is an element separation gap.
The commercial pressures on technology to make memories more dense have come to the point where a memory cell (such as in FIG. 18) consists of a single transistor contacted at its gate electrode by aluminum interconnect 288. But high speeds have not been possible because the ON resistance of the transistor itself does not proportionally drop when scaling down the overall device size.
The present invention solves the above problems, in at least one embodiment it does so by separating the Schottky diode construction from the material used to interconnect the memory cells in read sense columns. The vertical bit line lines can be heavily doped and thus can be highly conductive, even at very fine line widths.